Input Leakage Current of a GPIO | Cypress Semiconductor
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Input Leakage Current of a GPIO
The DC Electrical Characteristics for GPIO mentions "Gross Tested to 1uA" for the input leakage current. What does this mean? What is the minimum and maximum values for leakage currents for a psoc GPIO over the industrial temp range?
"Gross tested to 1 uA" is the combined leakage current of all the GPIOs. It is the the total current at the high limit of the temperature spec when all of the pins (except Vss, Vdd) are put in high-Z and tied together. Generally, if any one of the inputs is bad, it is over this limit, and we reject the die. Leakage failures tend to be gross, i.e., you don't have nominal leakages less than 1 nA, then a pin or two at 12 nA. If you get a bad one, it's over a microamp.
Examining the characterization of 5 different chips, the mean leakage value for all of them was less than 0.5 nA at 25 C. Some were as low as 55 pA, which is at the noise limiit of our test equipment. Since this is a leakage term, it follows the Arrhenius equation, doubling from the room temperature value every 10 degrees C, so if you had 0.5 nA worst case at 25 deg C, then at 100 deg C you could expect 0.5 nA * 2^(75/10) = 90.5nA, at 70 C (industrial temp) worst case would be 11.3nA.