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Input Jitter in Synchronous SRAMs | Cypress Semiconductor

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Input Jitter in Synchronous SRAMs

Last Updated: September 01, 2011

Does Synchronous SRAM like when interfaced with an FPGA sensible to cycle jitter OR does it accept everything as long as timing requirements are met?


The device can accept any kind of incoming jitter as long as the input timing parameters specified in the datasheet (especially set up and hold times) are met.

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