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Input Jitter Requirements for 65 nm QDRII/II+/DDRII/II+ Device Family - KBA84380 | Cypress Semiconductor

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Input Jitter Requirements for 65 nm QDRII/II+/DDRII/II+ Device Family - KBA84380

Last Updated: November 20, 2012

What are the input jitter requirements for 65 nm QDRII/II+/DDRII/II+ device family?


The performance of Cypress’s QDRII/II+/DDRII/II+ SRAM devices is dependent on its input jitter. The three critical timing parameters that must be met to guarantee proper operation are as follows:

  • K Clock Cycle Time (tCYC)
  • K Clock Rise to K# Clock Rise (tKHK#H)
  • Input Setup and Hold Times Referenced to K Clock

K Clock Cycle Time (tCYC): This parameter denotes the cycle time of the input K clock. If the cycle time of this clock at any instance goes below the minimum datasheet specification due to the input clock jitter, then the device may not function properly. Use the next higher speed bin to accommodate input clock non-idealities. For example, a 400 MHz SRAM has a minimum tCYC of 2.5 ns. If the system runs at 400 MHz with input clock jitter that drives tCYC down to 2.3 ns (or 434 MHz), then use the next higher speed bin, which is the 450 MHz speed bin.

K Clock Rise to K# Clock Rise (tKHK#H): This parameter denotes the time between the rising edge of the K clock and the rising edge of the K# clock. To ensure proper device operation it is critical that the tKHK#H parameter must never exceed the minimum value as defined in the datasheet.

Input Setup and Hold Times Referenced to K Clock: Under any input jitter condition, all setup and hold parameters must be met to guarantee operation. These include, tSA, tSC, tSCDDR, tSD, tHA, tHC, tHCDDR, tHD.

To summarize, any type or amount of input clock jitter does not affect device operation as long as the above critical timing parameters are met. Also note that the tKCVar (clock phase jitter) parameter does not affect device functionality if the above conditions are met. However, this parameter does have an impact on the jitter performance of the output data and echo clocks.

Jitter Performance

The 65 nm QDRII/II+/DDRII/II+ device family has a phase-locked loop (PLL) internal to the device. The PLL actively filters the incoming jitter of K clock to a certain degree depending on the jitter frequency component.

Jitter Transfer Function Measurement

Figure 1 shows the measured jitter transfer function. The X-axis represents the frequency component offset from the K-clock frequency (Fk). The Y-axis represents the amplitude of the jitter transmitted to CQ/CQ#. The plot represents the positive side of a band pass filter and indicates that any jitter with a frequency component outside Fk ±3 MHz will be heavily filtered.

Figure 1. Measured Jitter Transfer Function for QDR/DDR PLL Based Memories

Jitter Histogram Measurement

Figure 2 shows the output from an experiment in which jitter is injected to the K clock using a white noise source. The input clock frequency is 350 MHz. The experiment shows almost 6x reduction in jitter standard deviation (σ). This experiment was done to evaluate the PLL performance in filtering input clock noise and shows the performance improvement of PLL based devices. Additional noise is generated at the output clock during read/write operations to the SRAM.

Figure 2. (a) Noise Injected into K Clock (b) Noise Measured on Echo CQ Clock

PLL Implementation

Figure 3 shows a simplified diagram that explains the PLL based implementations. In the PLL implementation, CQ is generated from a voltage controlled oscillator (VCO) that is driven by a low pass loop filter. If jitter is injected to the input K clock, then the loop filter eliminates the high frequency components. Therefore, the VCO does not respond to that jitter and the CQ clock is kept at a steady phase.

Figure 3. PLL Based Implementation

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