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Initial State of PSoC 3/5 GPIOs during POR | Cypress Semiconductor

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Initial State of PSoC 3/5 GPIOs during POR

Last Updated: May 24, 2011

What is the state of the GPIO pins in PSoC 3/5 during POR?


The default state of the General Purpose IO pins in PSoC 3/5 is High-Z.  But this can be changed to either Pull Up or Pull Down, by modifying the "Power On Reset" parameter in the "Reset" tab in the GPIO configuration.

When the default state is changed in the cofiguration, this information is stored in the Non Volatile Latch (NVL) and the pin will be configured to the desired state during POR.  However, the NVL has very limited write cycles (1K at 25C and 100 at 0 to 70C).  Hence do not change the default state of a pin during the design stage to avoid failure of the NVL and the pin (see warning in the above screen shot).

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