Incorrect results from ADCs while debugging | Cypress Semiconductor
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Incorrect results from ADCs while debugging
Why do analog to digital converter (ADC) user modules return inconsistent and/or incorrect values when using the debugger to go through the code step-by-step, even when the measured voltage is a known, constant value?
In PSoC, ADC user modules are created by using a combination of SC Blocks and Counters. The SC blocks are configured as analog modulators and Counters are used to integrate the bit stream from the modulators. During normal ADC operation, the value from the counter is read after a specific number of integration cycles, for example for a 12 bit ADC, the value of the counter is read once every 4096 integration cycles. If the counter is not read after 4096 cycles, the counter will continue integrating into the next ADC cycle and the result will be corrupt.
During debugging operation, when the processor is halted, only the CPU halts. The ADC hardware keeps running in the background. If the CPU is halted, say for 5 seconds, the Counter would have been continuously running for those 5 seconds and naturally, when the value of the counter (which is the ADC result) is read, the result will be wrong. To get correct results from and ADC user module while debugging, following methods may be used.
- Try running the program continuously with the ADC continously getting measurements. Then, push the "Halt" button, and the program will pause at its current instruction. The variable that holds the ADC's result should now hold the correct result.
- Another method is to place a new break point where you want to halt while the program is running. A break point placed dynamically (while the program is running) will result in a break the next time the program passes that point.
- Store the data in an array and view the contents of the array after halting. In that case, only the first entry after a Run is hit will be corrupt.