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I2C Clock Permanently Stuck To Logical Low

Last Updated: June 15, 2010

Question:  Why PSoC permanently holds SCL line low after it sends an ACK to a received address byte ?

Response: Details given below,

  • Caused due to a bug in EzI2C user module code
  • Found in EzI2C user module version 1.2 shipped with PSoC Deisgner 5 SP5
  • Solution to this problem is to replace existing 'EzI2Csint.asm' template file from below locations with the one attached with this KB article,
    1. C:\Program Files\Cypress\Common\CypressSemiDeviceEditor\Data\CY8C20060\EzI2Cs
    2. C:\Program Files\Cypress\Common\CypressSemiDeviceEditor\Data\psoc_0100\EzI2Cs
    3. C:\Program Files\Cypress\Common\CypressSemiDeviceEditor\Data\Stdum\EzI2Cs


  • I2C SCL line is stretched to logic zero permanently from the PSoC side soon after master send a data byte following an address byte
  • Address byte send by the master is ACK'ed by the PSoC even if it is not its address

Root Cause:

  • Refer the attached 'pdf' file for details


File TitleLanguageFile SizeLast Updated
Download I2C Clock Permanently Stuck To Logical LowEnglish26.46 KB10/08/09
Download psoc_0100_EzI2CsInt.zipEnglish3.99 KB06/09/10
Download Stdum_EzI2CsInt.zipEnglish4.19 KB06/09/10
Download CY8C20060_EzI2CsInt.zipEnglish4.02 KB06/09/10

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