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HSTL compliance of QDR II SRAM | Cypress Semiconductor

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HSTL compliance of QDR II SRAM

Last Updated: May 13, 2010

Question: In the datasheet of  CY7C1514V18 , it is specified that it has variable drive HSTL output buffers. Will the device operate if High drive strength HSTL-II or HSTL-III are used?

Response:The CY7C1514V18 device uses the HSTL-I class output buffer. It is not completely compliant with HSTL-II. By variable drive HSTL output buffer, we mean that an external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching is between 175 and 350 thus varying output impedance between 35 ohms and 70 ohms. HSTL II compliance depends on what output impedance setting you use for the device (i.e. what resistor value you connect to the ZQ pin). For the nominal 50 Ohms output impedance setting, HSTL Class II is not met. All outputs of QDR-II are 1.5V Class I HSTL compatible

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