You are here

How to fix the Reset issue observed with AT2LP Revision C? - KBA89895 | Cypress Semiconductor

Support & Community

How to fix the Reset issue observed with AT2LP Revision C? - KBA89895

Last Updated: November 15, 2013

How to fix the Reset issue observed with AT2LP Revision C?


This article offers the solution for the reset issue seen by customers in the field when using the AT2LP Revision C chip

What is the issue and why does it arise?

In response to customer requests, Cypress reduced many delays in the time between reset and startup for the AT2LP chip. The delay reduction occurred when the AT2LP went from Revision B to Revision C. With this timing change, certain drives (in many cases ATAPI drives) hang the host during the boot up process or during a soft reset [Ctrl] [Alt] [Del].

Symptoms of the issue

This failure is only seen on Revision C of the AT2LP chip, Revision B chips do not exhibit this problem. The symptoms most commonly noted by customers are listed below. They only occur when using the AT2LP chip revision C and the default IIC file included in the AT2LP kit. The symptoms are as follows:

  1. The host hangs on boot-up when the external USB drive is set to be the primary boot device in the BIOS. Most of the time, the BIOS times out and continues to boot up but occasionally some do not.
  2. The host hangs when a reset is issued. In this case, most BIOS time out and continue to boot while others just hang.
  3. If you probe the ATA bus with an oscilloscope, notice that the RDIOR line is held low while the RDIOW line is held high. This is what causes the host to stop booting. Since RDIOR is active low, being held low indicates it is still active and the boot-up sequence cannot continue.


There are two parameters in the EEPROM that can change startup time:

  1. Delay after reset: The default value for this parameter (‘0’) creates a delay of 1000 ms between the drive reset and the first access to the drive. If this value is not ‘0’ then it can be used to adjust this delay in 20 ms increments. A value of 2 causes a (short) delay of 40 ms, while a value of 0x80 causes a (long) delay of 2560 ms. Please refer to Figure 1.
  2. Skip pin reset (address = 0x05, bit 0): Setting this bit to ‘0’ causes a hard reset of the drive on a USB reset. Some drives may require a hard reset to properly configure their interface after the host is powered down. Please refer to Figure 2.

The EEPROM settings should look similar to Figure 1 and Figure 2.

Figure 1: Delay After Reset Increased
Figure 2: Setting the Skip Pin Reset bit to 0.
Knowledge Base Tags: 

Provide feedback on this article

Browse KB By Product

Browse KB by Type