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High Signal on Compare Output When Period Is Changed in Firmware – KBA89231 | Cypress Semiconductor

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High Signal on Compare Output When Period Is Changed in Firmware – KBA89231

Last Updated: March 12, 2014

The compare output shows constant high pulse when using the counter in Up Counter clock mode and updating the period value in the firmware. Why does this happen?


You will see this error if you load the period register with a value lesser than the previous period value when the count register value is greater than the new period. When Clock Mode is set to Up Counter and Reload Counter is set to On TC, the counter value is reloaded with "0" when it overflows. However, when the new period value is less than the currently running count register value (which is less than the old period value), the counter will count up to ((2^Resolution)-1) and then reload to 0—for example:

Default period = 0x09;

Counter: 0x00 0x01 0x02 0x03 0x04 0x05 0x06 (set new period = 0x05) 0x07 0x08 0x09 (here the counter should be reloaded by "0", but the counter will count up to
((2^Resolution)-1)) 0x0A 0x0B 0x0C … ((2^Resolution)-1) 0x00.

In the Up Counter mode, you should disable the counter before writing the new period value. After that, you should set the count register to "0" and enable the counter. Or you can set Clock Mode to Down Counter to avoid this situation.

Thus, instead of using the following code snippet:

Counter_WritePeriod(40); // Suppose previous value was 100

You should use this one:

Counter_WriteControlRegister(Counter_ReadControlRegister() & ~(Counter_CTRL_ENABLE)); // disable counter

Counter_WritePeriod(40); // write new value of period

Counter_WriteCounter(0); // set counter value to zero

Counter_WriteControlRegister(Counter_ReadControlRegister() | Counter_CTRL_ENABLE); // enable counter

This component issue is being worked on.

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