High-capacitance load on CLKOUT pin of FX2LP | Cypress Semiconductor
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High-capacitance load on CLKOUT pin of FX2LP
My design interfaces a high-capacitance load to the CLKOUT pin of FX2LP. I’m not sure about the effect on the rise-time and fall-time of the signal due to this. How do I evaluate whether I can directly interface with the pin or if I should add a buffer on the line?
When connecting high-capacitance load to the CLKOUT pin one thing to be kept in mind is that the 4mA source/sink current of the pin is not exceeded. Then simulations can be run using the IBIS model to have an estimate of the signal timings. Based on these two conditions it can decided whether a buffer is needed on the line.