Handling of USB bus reset by External master interfaced to SX2 | Cypress Semiconductor
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Handling of USB bus reset by External master interfaced to SX2
How does the external master handle the case where SX2 receives a USB bus reset?
When the SX2 detects a USB Reset condition on the USB bus, SX2 handles it like any other enumeration sequence. This means that SX2 will enumerate again and assert the ENUMOK interrupt to let the external master know that it has enumerated. The external master should then configure the SX2 for the application. The external master should also check whether SX2 enumerated at High or Full speed in order to adjust the EPxPKTLENH/L register values accordingly. The last initialization task is for the external master to flush all of the SX2 FIFOs.