Glitch on P1 at POR and XRES | Cypress Semiconductor
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Glitch on P1 at POR and XRES
After POR or XRES event, P1 goes high for some time. Why is it so?
All GPIO pins in the PSoC are in the HighZ state during POR or XRES reset events. But Pins P1 and P1 are ISSP pins and respond differently to a POR or XRES event than other IO pins.
At power up, the internal POR causes P1 to initially drive a strong high (1) while P1 drives a resistive low (0). After 256 sleep oscillator cycles (approximately 8 ms), the P1 signal transitions to a resistive low state. After additional 256 sleep oscillator clocks, both pins transition to a high impedance state and normal CPU operation begins.