Glitch on the I2C Lines During Power Up | Cypress Semiconductor
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Glitch on the I2C Lines During Power Up
Why is there a glich on the I2C lines during Power On or Reset? How can this be removed?
There are different reasons for the glitch on the I2C lines during Power On.
P1 and P1 : These lines are used for ISSP as well, so they behave differently as compared to other pins on power up or after reset. At power up, the internal POR causes P1 to initially drive a strong high (1) while P1 drives a resistive low (0). After 256 sleep oscillator cycles (approximately 8 ms), the P1 signal transitions to a resistive low state. After additional 256 sleep oscillator clocks, both pins transition to a high impedance state and normal CPU operation begins.
During External Reset (XRES=1), both P1 and P1 drive resistive low (0). After XRES de-asserts, these pins continue to drive resistive low for another 8 sleep clock cycles (approximately 200 us). After this time, both pins transition to a high impedance state and normal CPU operation begins. The glitch caused because of this hardware design cannot be avoided. So, if this causes problem on the I2C bus, use P1 and P1 instead for the I2C communication.
When the Drive mode of the pins is set to Open Drain Low in the psocconfigtbl.asm, the I2C pins will be driven LOW because the Bit5 and Bit7 in PRT1DR are 0. The pins are pulled high when the I2C hardware is enabled in main and the pins get connected internally to the I2C hardware. Following are a few workarounds for this problem.
1. Add following lines of code in psocconfigtbl.asm file just before the drive mode of port 1 is set:
or reg[PRT1DR], A0h
This will set the value of Bit5 and Bit7 in PRT1DR register to 1. This will result in the pins pulled high when the drive mode is configured to Open Drain Low. But this solution has a problem that every time the source is generated in PSoC designer, the modification to the psocconfigtbl.asm file will be lost.
2. Add the same instructions in boot.tpl before the call to LoadConfigInit function. The changes made to boot.tpl will reflect in the boot.asm file every time source is generated and the modification will be preserved.
3. The third and easiest work around is not to configure P1 and P1 as Open Drain Low. Just leave them as Hi-Z Analog (or explicitly set them as Hi-Z Analog in the GPIO configuration window). Then, in main, write a 1 to Bit5 and Bit7 of PRT1DR and then configure P1 and P1 as Open Drain Low by writing to the PRT1DMx registers.
The reason for glitch and the work arounds for P1 and P1 apply to P1 and P1 as well.