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FullFlex - Echo clocks and their timing benefits | Cypress Semiconductor

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FullFlex - Echo clocks and their timing benefits

Last Updated: June 11, 2011

Explain Echo clocks for FullFlex Dual ports SRAM's? What are their timing benefits?


Echo clocks and why we need them:


With high speeds driving the electronic industry, on board delays (clock skew) caused by parasitic make accurate clock trees extremely difficult. In particular, the Dual Data rate (DDR) environment requires tighter timing control. Echo clocks were designed to counter this problem.



How does it work?


The Dual port receives input clock (C for SDR and C, C# for DDR) at its corresponding pins. On a read operation the input clock is used to clock in the address and the control signals. The dual port then buffers this clock and retransmits it synchronous to the data output. Each port has 2 pairs of echo clocks. The CQ1 and CQ1# outputs are associated with data pins [71:36] and the CQ0 and the CQ0# is associated with data [35:0]. The DP also has echo clock enable (CQEN) at both the ports. So, the option can be set on a per port basis by tying the corresponding CQEN pin to Vdd. Echo clocks are Hi-Z in the flow through mode (Flow through mode works only with SDR). The figures attached show the echo clock delay for SDR and DDR modes. 

File TitleLanguageFile SizeLast Updated
Download SDR.JPGEnglish8.66 KB04/01/09
Download DDR.JPGEnglish12.37 KB04/01/09
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