Full Flag De-assertion in FIFOs of FX2LP | Cypress Semiconductor
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Full Flag De-assertion in FIFOs of FX2LP
When is Full Flag de-asserted? Is it after one byte/word is sent to PC or after the entire FIFO bytes/words are sent to PC?
The FULL flag will be deasserted when one byte/word is sent to PC and not after the entire FIFO bytes/words are sent to PC. The external master needs handshaking signals to manage under-flow or over-flow conditions.
Typically an external master will look at the FIFO full flag when writing data into FX2LP to decide when to stop writing, and will look at the FIFO empty flag when reading data from FX2LP to decide when to start reading. So you should not write to a FULL FIFO and should not Read from an Empty FIFO.