Frequency Selection in CY22393/4/5 | Cypress Semiconductor
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Frequency Selection in CY22393/4/5
S0 and S1 are being referred to as frequency select lines but they are not visible in CyberClocks. The data sheet says they are SDAT and SCLK but also S0 and S1. Please clarify.
In the Pin Summary table on page 4 of the datasheet, it is stated that pins 12 and 13 are I2C SDAT and SCLK respectively during normal operation and they act as S0 and S1 respectively, at start up. S2, S1 and S0 constitute frequency selection control pins to select either of PLL1 frequency arrays 0 (000) through 7 (111). What happens is that since S2 is the only frequency select control pin you have during normal operation, CyberClocks sets the first four frequency arrays Table0 through Table3 to the same configuration corresponding to S2 = 0. It sets the second set of four tables 4 (100) through 7 (111) to the second frequency configuration option. therefor, regardless of the status of S1 and S0 at start up, there are only two frequency selections controlled by S2.
For programming using SDAT and SCLK, however, any of the 8 tables (refer to the table below) can be written to. Write must be made only to the table pointed to by the latched state of S2,S1 and S0. This is the state of the three lines at start up.
If SDAT (S0 at start up) and SCLK (S1 at start up) were pulled to 0 and 1 respectively during start up, then only blocks 010 and 110 can be written to during normal operations. Toggling S2 will then select between the two configuration options.
Assume at start up the state of S0 is 0 that of S1 is 1 and S2 is 0. The frequency table 010 (2) is loaded for normal operation. Since this configuration is the same as table0, table1 and and table3, any combination of the initial states of S0 and S1 would load the same configuration. Now, assume S2 is 1 and the states of S1 and S0 at start up is 01. Then table 101 (5) is loaded. But, since this configuration is common for all tables 4, 5, 6 and 7, again, the state of S0 and S1 does not matter.
So, the bottom line is SCLK and SDAT status at start up is "DON'T CARE". All that matters for frequency selection between two configurations is S2. The loss of S1 and S0 control is, however, mitigated with the flexibility the two wire I2C offers to shift different configurations into the SRAM on the fly.
The table below illustrates the discussion above.
|External Ctrl Pin S2||S1S0 Status at Power Up||Selected Frequency Tables Based on the State of S2 and that of S1 & S0 at start up|