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Flow Control in Slave FIFO - KBA90276 | Cypress Semiconductor

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Flow Control in Slave FIFO - KBA90276

Last Updated: January 30, 2014

How does the FX3™ achieve flow control in slave FIFO?


The main purpose of any GPIF™ II design is to manage data transfers into and out of the FX3™ device's buffers. Therefore, dealing with DMA buffer readiness and performing flow control is an essential part of these designs. The FX3 device makes use of a number of DMA buffers of programmable size to send/receive data across the GPIF II interface. There is a small time frame where it cannot transfer data because the active DMA buffer is being switched. It is also possible that the DMA buffer is not ready for transfer when the external processor is trying to initiate a transfer. The FX3 device provides a set of DMA status flags that can be output on select GPIOs and used to perform flow control on the processor side. The DMA status flags can reflect one of the following:

  • DMA ready status - buffer empty/full indication.
  • Data count above/below user programmable threshold indication. The FX3 firmware API must be used to set the threshold value for various buffers.
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