Floating I/O Pins on Async FIFO | Cypress Semiconductor
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Floating I/O Pins on Async FIFO
Can the data input pins of an asynchronous FIFO be left open? Can the data output pins of an asynchronous FIFO be left floating? If I have only an 8-bit processor and a 9-bit wide data bus, what should I do with the unused bit?
The data input pins of Cypress asynchronous FIFOs should not be left floating. However, if it is not possible to pull the unused pins to Vcc or GND, then the data written into the FIFO from these pins will not be guaranteed so these bits should be considered as "don't care" values.
For example, a 32-bit data width FIFO has 20 of its data input pins connected to a device with the other 12 pins left floating. When data is written into the FIFO from the 20 data pins, that 20-bit data is stored in 20-bits of a 32-bit wide memory location. Unknown "Data" from the 12 floating pins is written into the other 12-bits in the 32-bit memory location. As a result, the 32-bit word of data in that specific memory location has 12 of its bits which have unknown values, which can cause data to be "corrupt".
A general rule that should never be broken is that input signals should not be left floating. Depending on what that input signal is, you should pull the input to a known value (either Vcc or GND). This is also true of I/Os (signals that are both input and output). These signals should be pulled high or low with a resistor to some known value if you are not going to be using it.
On the other hand, output only pins like the data out pins of the FIFO can indeed be left floating. Data outputs (Q) are in high-impedance state when R# is high or when the FIFO is empty. It is ok to attach weak pull up/down resistors at the system designer's choice.
The above discussion applies only to unidirectional FIFOs.