EZ-USB suspend condition | Cypress Semiconductor
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EZ-USB suspend condition
How is the suspend condition implemented for the EZ-USB?Is the suspend condition for the EZ-USB interrupt driven?
Typical steps of inplementation are:
A Global Suspend (3 ms with no USB activity) causes an 8051 interrupt, the EZ-USB vectors directly to the ISR.
The 8051 does any required housekeeping (like shutting down external subsystems, typically in the Suspend ISR).
The 8051 enters the 'idle' state by setting bit 0 in the PCON SFR.
An 'idle' signal from the 8051 core signals the EZ-USB core to shut down.
The EZ-USB core stops the 24 MHz clock for low quiescent current.
Note: The 8051 needs to see a global suspend event occur BEFORE it can put the part into low power mode (IDLE).