EZ-Host/OTG harware connections required to come out of reset and begin executing BIOS | Cypress Semiconductor
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EZ-Host/OTG harware connections required to come out of reset and begin executing BIOS
What are the bare minimum standalone hardware connections required for EZ-Host/OTG to come out of reset and start executing BIOS?
1. 12MHz clock or crystal that matches datasheet?s specs.
2. Power on reset (low signal) of at least 10ms, as indicated in datasheet.
3. EZ-Host Only: Pull-up resistor (47K) on EZ-Host pin 38, A15/CLKSEL pin.
4. Ground all reserve pins (pin 48 on EZ-Host, pin A6 on EZ-OTG).
5. Set GPIO[31:30] appropriately.
6. Make sure VCC, AVCC, and BoostVCC are all connected to power.
7. Make sure that both GND and AGND are grounded.
When EZ-Host/OTG properly comes out of reset, code execution will begin at 0xFFF0 with an immediate jump to 0xE000, which is the start of BIOS. During BIOS initialization, BIOS will make read operations to both the I2C bus and external memory interface (EZ-Host only) to see if there is code to be loaded. Therefore, either the SDA pin on the I2C interface or the nRD pin of the external memory can be probed for activity to ensure that the part properly exited reset and began BIOS code execution.