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Events causing Soft Error Rate (SER) in Sync SRAMs

Last Updated: September 01, 2011

What are the various events causing Soft Error Rate (SER) in Sync SRAMs?


Soft Error Rate (SER) is defined as the probability that a device will fail, normally using units of FIT (Failure in Time) which are fails per 10^9 hours. The following is a list of the major single event effects (SEEs) phenomena and their definition:
Physical Single Bit Upset (PSBU): This failure type involves a single particle causing only a single memory cell of the memory array to fail.

Physical Multi Bit Upset (PMBU): A single particle causing more than one bit to fail in the physical memory array. To the contrary a Multi Cell Upset (MCU) describes only the event itself and does not further specify how many bits are upset. This failure type involves more than one cell in the physical memory array changing their state. Typically, it can involve two to several hundreds of bits depending on the particle.

Logical Single Bit Upset (LSBU): Number of failing memory bit in the data word caused by a single event. LSBU’s represent the true failure rate of the part as seen from the application level.

Logical Multi Bit Upset (LMBU): More than one bit failing in a data word caused by a single event.

Single Event Latchup (SEL): Circuit latchup caused by a single radiation particle. An SEL may or may not cause permanent device damage, but requires power cycling of the device to resume normal operation.

Please note that significant measures have been incorporated on the Cypress SRAMs to mitigate the impact/prevalance of SER/SEL events.

The values for the above parameters can be found in the respective product datasheets under the section, "Neutron Soft Error Immunity" next to the "Maximum Ratings" section of the datasheet.

For more details refer to Application Note AN 54908 "Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates"


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