Endpoint/FIFO Configurations for FX2LP | Cypress Semiconductor
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Endpoint/FIFO Configurations for FX2LP
What is the typical sequence of events when an external master writes data into the FIFO which is configured in the following configuration?
1) EP2IN (Iso, 4x buffered, using the entire FIFO space)
2) EP2FIFOCFG configured for byte wide operation, 1024 physical size
3) EP2AUTOINLENH/L setup for 1024 (so FX2 is in auto mode)
4) External master looks at the status of EP2's FIFO full flag.
Assuming that the host has not asked for the data first, here's the typical sequence of events:
1) External master writes 1024 bytes (packet 1) into the FIFO and packet 1 gets committed to the USB side (full flag not yet asserted.)
2) External master writes packet 2 into the FIFO and packet 2 gets committed to the USB side (full flag not yet asserted.)
3) External master writes packet 3 into the FIFO and packet 3 gets committed to the USB side (full flag flag not yet asserted.)
4) External master writes packet 4 into the FIFO and it gets committed to the USB side (full flag is asserted some time after.) See datasheet.
4) External master writes the 1024th byte in packet.
5) External master sees the full flag assert and stops writing data into the FIFO.
6) External master cannot write data into the FIFO until the host takes off one packet. The full flag continues asserted until a full packet is available, at which point the full flag deasserts and the external master can write another packet into the FIFO.