Echo Clocks Usage QDR and DDR Synchronous SRAM families | Cypress Semiconductor
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Echo Clocks Usage QDR and DDR Synchronous SRAM families
What is the Echo clock?
Echo Clock is a free running clock which is frequency locked via a PLL or DLL to the input K Clock. It is edge-aligned with the Data output from the memory. It is the clock that is used to clock out the data. It therefore tracks the data much better than the K clock. The source of the Data output and Echo clock is the same PLL/DLL. The Echo clock jitter tracks very closely with the Data output jitter.
To create a strobe which is used by the memory controller, the echo clock is delayed by 90 degrees to ensure that the input data is latched at the center of the data eye. This is usually achieved by internal delay lines that step through different delays to ensure that the strobe (echo clock) is placed at the center of the Data input. Alternatively a constant delay could be achieved by delaying the clock by a known amount on the PCB by introducing a finite trace delay.
Please refer to the pin definitions section of the appropriate data sheet as well as the Switching Characteristics section for more information on these pins. For a more detailed application usage of Echo clocks please refer to the Clocking Strategies section of AN-4065.