Duty Cycle for CY2309NZ | Cypress Semiconductor
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Duty Cycle for CY2309NZ
The CY2309NZ datasheet specifies a 40-60% duty cycle. Does this mean that with an input clock with variable duty cycle the part will be corrected to a 40-60% duty cycle output?
CY2309NZ is a simple fanout buffer. There is no duty cycle correction circuitry. Therefore, if a non-50% duty cycle input clock is used, the buffer outputs will attempt to follow the input signal, limited only by the frequency and slew rate capabilities of the output driver versus the input. Naturally, there are many cases when the output cannot track the input, e.g. an input pulse << Tr+Tf. In order to ensure the device outputs meet the 40%-60% duty cycle spec, the reference input should have 50% duty cycle.