Drive Mode of GPIO Pins at POR | Cypress Semiconductor
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Drive Mode of GPIO Pins at POR
What is the drive mode of the GPIO pins during the POR state?
Immediately after the POR event, all the GPIO pins except P1 and P1 are in High Impedance state. They remain in this state till they are reconfigured according to project settings in the psocconfigtbl.asm file.
At power up, the internal POR causes P1 to initially drive a strong high (1) while P1 drives a resistive low (0). After 256 sleep oscillator cycles (approximately 8 ms), the P1 signal transitions to a resistive low state. After additional 256 sleep oscillator clocks, both pins transition to a high impedance state and normal CPU operation begins.
More details with timing diagrams may be found in the Technical Reference Manual Section 30 >> System Resets >> GPIO Behavior During Reset
This applies to the following families of PSoC:
CY8CPLC20, CY8CLED16P01, CY8C29x66,CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A,CY8C22x13, CY8C21x34, CY8C21x23,CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953