Dividing the memory array into upper and lower bytes in the CY7C02X / CY7C03X family | Cypress Semiconductor
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Dividing the memory array into upper and lower bytes in the CY7C02X / CY7C03X family
- What happens to the semaphores when one divides the memory array into upper and lower bytes in this family of dual-ports?
- What can possibly cause contention on the data bus?
In the CY7C02X/CY7C03X family of asynchronous dual-ports, the data can be divided into upper and lower bytes. For example, in the CY7C024, 16 bits can be divided to form an 8 bit data line controlled by the LB (lower byte) and UB (upper byte) control signals. However, in this setup, the semaphores can be problematic. Because of small internal delays, bus contention may occur on the data bus. If the dual-port is operated infrequently, this should not be a problem. In the situation where contention occurs, to avoid the occurrence of high current drawn, put 50/100-ohm resistors (in series) on all data lines.