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Depth and width expansion affect on board-level timing | Cypress Semiconductor

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Depth and width expansion affect on board-level timing

Last Updated: June 11, 2011

How does memory depth and width expansion affect board-level timing?


In both depth and width expansion, address, data, clock and most control signals are routed in parallel to multiple dual-port devices.  Each dual-port input has an associated input capacitance.  Therefore, the total input capacitance is multiplied by the number of devices used in the expansion.  This will slow down the edge rates at the dual-port inputs.  The external device(s) that are driving address, control, and clock signals to the dual-ports will have output timing parameters that are associated with a specific test load.  If the combined input capacitance for each signal exceeds the driver test load, the driver's output parameters can no longer be guaranteed.  In this case an IBIS model simulation is recommended to assure the required system timing can be met. Depth expansion presents another board-level timing concern because there are multiple devices on the data bus and data is bi-directional.  The case where data is written to the dual-port is covered above.  When data is read from the device, the dual-port output driver has to drive the same capacitance.  Like the external driver, the dual-port's output timing parameters are guaranteed assuming a certain test load.  If the actual load exceeds the test load, the output parameters are no longer guaranteed.  An IBIS model simulation is also recommended for this case. 

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