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Default Stae of GDx and PWx Pins at Power Op or Reset - CY8CLED04D01 | Cypress Semiconductor

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Default Stae of GDx and PWx Pins at Power Op or Reset - CY8CLED04D01

Last Updated: March 27, 2011

What is the default state of GDx and PWx pins of CY8CLED04D01 at power up or during reset?


Status of GDx and PWx pin depends on whether the power blocks are populated/started.

1) The power blocks are not populated or started - In this case, the internal FET will remain off and the external gate driver will be pulled to ground thereby keeping any external FET connected off.

2) The power blocks are populated and started - If the hysteretic controller is started before the Current Sense Amplifier (CSA), then for a brief period, there is an indeterminate signal going as feedback into the hysteretic controller. This could possibly switch the FET ON (or keep the external gate driver on) for a long period until the CSA powers up and the correct feedback is received. This is potentially a dangerous situation as the current could rapidly increase through the FET.

For this reason, the CSA should always be turned on before the hysteretic controller and the hysteretic controller should never be turned on without a proper feedback connection.

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