Data valid period during two consecutive read cycles with the same address | Cypress
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Data valid period during two consecutive read cycles with the same address
During a flow-through read cycle, your datasheets specify that tCD1 after the rising edge of the read CLK, data is ready to be read. They also specify that the data will remain valid for tDC. My question is what would happen if you perform two flow-through read cycles with the same address consecutively? The datasheet shows a data valid period followed by unknown data followed by the data valid period for the following read. Does this apply to this case? Or will the same valid data from the first read remain on the data lines until the end of the second read cycle?
The same valid data would remain on the data lines until the last read cycle perform to the same address. Since the input address for our dual port memory is exactly the same in both reads, there is not a time where internal circuitry attempts to drive data lines to different states. Therefore that same data will remain on the data lines without any switching glitches. You are free to sample the data lines tDC after the data is first valid in this case.