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CY7C68001-Ready Signal | Cypress Semiconductor

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CY7C68001-Ready Signal

Last Updated: June 10, 2011

Would it be better to check the rising edge for Ready rather then doing a level sensitive check?


The key thing is that command writes always need to be gated by an active high ready signal. Note that there is a difference between the ready signal and a ready interrupt. The best method is to program the input pin on the host processor to be rising-edge sensitive. This will guarantee that you do not perform multiple writes before the ready signal has gone low and come back up again. You could also add a fixed delay in between writes (10us should be enough) so you do not examine the ready signal until 10us later. At that point the ready signal should be high again.

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