CY7C68001 EZ-USB SX2 INT# Pin Behavior for Multiple Interrupts. | Cypress Semiconductor
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CY7C68001 EZ-USB SX2 INT# Pin Behavior for Multiple Interrupts.
The EZ-USB SX2 is capable of buffering multiple interrupts and INT# should be asserted if there is one or more pending interrupts. Must multiple interrupts be captured by an edge-triggered or level-triggered interrupt pin on the external master? For example, when there are two pending interrupts, reading the interrupt status byte clears the first interrupt. However, there is still one more pending interrupt, so the INT# line should be asserted again.
INT# ___/ \__
Which waveform is correct?
The first waveform is the correct behavior. Therefore, it is best if the INT# signal is sensed on the falling edge (negative edge triggered). The external master's interrupt sense pin should be edge-triggered.