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CY7C08xxV Read Cycle Latency | Cypress Semiconductor

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CY7C08xxV Read Cycle Latency

Last Updated: June 11, 2011

- Why is there no FT/PL pin in some of the synchronous dual-ports?
- What is the latency associated with read operations?


Unlike smaller synchronous dual-ports offered by Cypress, the CY7C08xxV family of dual-ports are all pipelined. There is no FT/PL pin because all of these devices are always in pipelined mode. This is because pipelined operation allows for faster operating frequencies. In the case of the CY7C0831V, CY7C0832V, CY7C0851V, and CY7C0852V devices, pipelined operation allows up to 167MHz operation. The trade-off is that the data from a read operation does not occur until after the following clock cycle. So if a read operation was requested on clock cycle 1, the data does not appear on the data bus until tCD2 after clock cycle 2. This is what is referred to as the read latency. Write operations are not different for these dual-ports. There is no latency associated with write operations.

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