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CY3280-22X45 DVK – KBA83007

Last Updated: April 08, 2014

Why is GPIO P1.7 in the CY3280-22X45 DVK not working properly?


The GPIO P1.7 in the CY3280-22X45 DVK is directly mapped to the Rx of the UART-level converter IC [MAX3232EEAE], which will be driving the GPIO with a logical high signal when in idle mode.

  • When you drive this pin low, a voltage divider is formed between the Rx pin and P1.7 port through R37 and the output impedance of MAX3232EEAE, which makes the port voltage nonzero.
  • When you drive this pin high, we will get normal high logic at the output.

Workaround: If you need to use P1.7 as a GPIO, de-solder the R77 resistor from the DVK. Note that removing R77 will render the Rx of UART unusable.

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