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CY23S09 Behaviour in PLL Bypass Mode | Cypress Semiconductor

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CY23S09 Behaviour in PLL Bypass Mode

Last Updated: June 19, 2011

Why there is no output when using the CY23S09 in PLL bypass mode, S2 = 1 and S1 = 0?




has a low frequency detector which determines if the input clock is below a certain period. If the input clock period is greater than this detected point, the output buffers are disabled and placed in the Hi-Z mode. When in normal PLL mode the low frequency cutoff point is between 3 and 5 MHz. The datasheet states that when the device is configured for PLL bypass mode, S2 = 1 and S1 = 0, the output clocks are driven by the Reference clocks. The low frequency detect circuit is also active in PLL bypass mode and will place the outputs in the Hi-Z mode when the input is lower that this detected frequency point. Whe using a pulse train, such as a burst of pulses and then a period of no clock pulses, the period of missing clock pulses can cause the output drivers to go into the Hi-Z mode. When being clocked by a pulse train with a period of missing pulses, the period of time of the missing pulses to shut-off the output drivers is > 750 ns. or 1.33 MHz. The


datasheet does not specifically describe this fact. Specifically, that the low frequency detect circuit works in both the PLL mode and the PLL bypass mode.

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