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CY22381, CY22392, CY22393, CY22394, CY22395 Input Requirements – Frequency, Jitter and Duty Cycle | Cypress Semiconductor

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CY22381, CY22392, CY22393, CY22394, CY22395 Input Requirements – Frequency, Jitter and Duty Cycle

Last Updated: August 07, 2014

What is CY22381FI's input freq tolerance (and jitter, duty cycle tolerance, etc.) for the PLL? In my application, the external input oscillator to CY22381FI will be in a high shock environment and may experience frequency instability for a uncertain period of time.


This answer applies to the CY22392, CY22393, CY22394 and CY22395, as well as the CY22381.

The external input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2 as mentioned in Note 2 on page 4 of 9 of the CY22381 Datasheet available on our website.
While the CY22381 is capable of accepting a wide range of input frequencies, the configuration software will configure the part only for a single specified input frequency.  Depending on the particular configuration, the part may or may not have tolerance to the specified input freqency.  Input frequency tolerance is not documented.
The internal PLLs act as a low pass filters.  Their bandwidth is configuration dependent, but is generally in the 200 kHz range. Input jitter above this frequency will be filtered and will not appear at the outputs. Slower input frequency changes, within this bandwidth, will be tracked and will be reflected in the outputs.
In the case of an oscillator subjected to shock, we would expect noticeable but not drastic frequency changes, of a transitory nature.  In this case, the CY22381 will attempt to track the slower frequency changes, and will likely cause some changes to the output frequency.  As long as the input doesn't become seriously unstable for an extended period of time - perhaps a thousand or more clock cycles - the PLLs and outputs will remain generally stable.

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