Constraints and Interchangeability of Data and Address pins in Async SRAMs | Cypress
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Constraints and Interchangeability of Data and Address pins in Async SRAMs
Can I interchange the address pins in Cypress Async SRAMs ? Or Can I interchange the data pins in Cypress Async SRAMs ?
Likewise, data lines can be assigned in any order, within a specific byte. For instance, D0 of CPU can be connected to D4 of SRAM, D1 of CPU to D6 of SRAM etc. However, the data bit assignment should not cross byte boundaries if byte level accesses are made. For instance, a higher bit data of CPU connected to lower bit data line in SRAM could result in conflict when performing byte-specific (lower byte or higher byte) accesses. If such individual byte-level accesses are not made, routing can extend beyond byte boundaries also.