Connecting SX2 SLOE and SLRD together | Cypress Semiconductor
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Connecting SX2 SLOE and SLRD together
Can the two signals SLRD and SLOE specified in REVD version of the SX2 datasheet be tied together as there is no timing restriction between them.
The SLOE and SLRD are two separate input signals. But based on the application needs these may be tied together. From the timing diagrams in the datsheet,the tOEN (SLOE Turn-on to FIFO Data Valid) is always less than tSRD (setup time for SLRD) for a synchronous read. For asynchronous read, tOEN (SLOE Turn-on to FIFO Data Valid) is also always less than tXFD (SLRD to FIFO Data Output Propagation Delay). So as long as the SLOE is enable when SLRD is asserted, it should be fine and the two can be tied together for the purposes of certain applications where the external master does not have either RD# or OE# signal output control signal.