Connecting SCBLOCK output to SAR6 | Cypress Semiconductor
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Connecting SCBLOCK output to SAR6
What should be the clock phase set to of the SCBLOCK feeding signal into SAR6 ADC?
Usually, when an output of an SC Block is connected to an input of an ADC, the clock phase of the ADC is set to swapped. This is because the output of an SC Block is valid during Phase-2 and is AGND in Phase-1. Setting the clock phase to swapped will ensure that the ADC samples the output of the SC block in Phase-2 and will have a valid result. Alternately, the clock phase can be set to swapped in the SC Block which is the source to the ADC as well. This applies to all ADC's with input connected to Amux.
But in case of SAR6, the input is applied to Bcap and the input by default, is sampled during Phase-2. Also, the SAR6 does not have a ClockPhase parameter. Set the clock phase of MDAC to Norm. This way, the output of the MDAC will be valid during Phase-2 and the SAR6 will sample the MDAC during Phase-2.