Complementary PWM Outputs with Dead Time on PSoC® 4 - KBA87491 | Cypress Semiconductor
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Complementary PWM Outputs with Dead Time on PSoC® 4 - KBA87491
How do you get complementary PWM outputs with dead time on PSoC® 4?
If you design your PWM generator with dead time, using Timer Counter PWM (TCPWM) in PSoC Creator™, you can set the component as shown in the following diagram.
Note that you can achieve the same target using the manual registers setting (refer to the PSoC 4 TRM). However, we recommend the first approach.
In Dead Time Insertion mode, the rising edges in the complementary PWM outputs, line and line_n, are delayed. The delayed time is based on the dead time setting, which ranges from 0 to 255 cycles. (0 is meaningless in practice). Be careful because if you introduce dead time, it changes the duty cycle. Recalculate to make sure you meet the needs of your design.