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Clock Ratio Specifications for High-Density FIFO (HDFIFO) - KBA88198 | Cypress Semiconductor

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Clock Ratio Specifications for High-Density FIFO (HDFIFO) - KBA88198

Last Updated: September 18, 2014

What are the Clock Ratio specifications for HDFIFO?


As specified in the device datasheet, both read (RCLK) and write (WCLK) clocks should be free-running. Also, the WCLK-to-RCLK ratio should be in the range of 0.5 to 2.

The Phase relationship between the read and write clock may be asynchronous. Because of this the FIFOs may receive both a read and write operation almost simultaneously. If the read operation is performed first, then the part becomes empty just before a word is written to it. At this point the device is waiting for a flag update cycle and one read cycle is essentially lost. If the write operation occurs just before the read, then the device has two words in it for a quick instance and then returns to having one word. Note that no flag update cycle is needed as the FIFO never became empty.

Also note that the latency table given in the datasheets holds true only when RCLK=WCLK, which means the clock ratio is 1. The latency values can vary with respect to the clock ratio between RCLK and WCLK as the computations are performed under two clock domains. The latency values given in the datasheet are guaranteed provided the clock ratio is 1.

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