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Clearing the mailbox interrupt | Cypress Semiconductor

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Clearing the mailbox interrupt

Last Updated: March 27, 2011

- How to clear the interrupt signal ?
- How to use the mailbox feature?
- What is min value of time when an interrupt is observed to the time when the interrupt is cleared?


The last two memory locations in synchronous dual-ports are reserved for mailbox messages to pass messages from a port to another port. When Port A writes data to Port B's mailbox location, Port B will get an INT signal to alert the processor that there is a message there. The mailbox is only cleared when port B reads its mailbox. The INT signal is updated on Port B's clock cycle. If Port B wants to send a message to Port A, it can do the same thing to Port A's mailbox location.

In general, the very last memory location is the mailbox for the right port and the second to last memory location is the mailbox for the left port.

Once the interrupt on a given port is activated, there is no required time interval that you must wait before writing to the interrupt flag to deassert the interrupt signal. There are timing parameters involved in the assertion and deassertion of the interrupt signal, and the reading and writing of memory locations.

The originating port cannot clear the opposite port's interrupt by reading from the opposite port's mailbox.

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