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Clearing of FIFO's in UDB | Cypress Semiconductor

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Clearing of FIFO's in UDB

Last Updated: December 28, 2011

How can the FIFO's in UDB be cleared?


Each UDB has two 4 byte deep FIFO's (F0 and F1) inside the datapath. The contents of the FIFO are automatically cleared when the FIFO's are read by the system bus. But in order to clear or flush the contents of the FIFO without reading them, the auxiliary control working register should be used.


The FIFO0 CLR and FIFO1 CLR bits of the auxiliary control working register are used to reset or flush the FIFO. When a '1' is written to one of these bits, the associated FIFO is reset. The bit must be written back to '0' for FIFO operation to continue.

The format of the register is as follows:


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