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CE not present in some Dual port SRAM's E.g CY7C0853V | Cypress Semiconductor

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CE not present in some Dual port SRAM's E.g CY7C0853V

Last Updated: June 11, 2011

- How do I enable and disable this dual-port since there are no Chip Enable (CE#) pins?

- If I have R/W# tied low on one side (always writing), how can I stop it when I need to?


The CY7C0853V does not have Chip Enables. Instead you can use the 4 Byte Enables (B0-B3) pins on each port to mimic the same function. So if you want to disable reads and writes to the dual-port, you can have B0#-B3# high. This will "disable" all memory accesses. It is the same circuitry as CE#.

It is not recommended to use only the Output Enable (OE#) signal to control memory accesses. Disabling OE# will indeed disable any read data, but it will not stop writing data into the memory. It is okay to disable the OE# signal in addition to B0#-B3# during read operations, but even if you do not, the data bus is tri-stated when none of the byte enables are selected.

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