Calculating the maximum input signal frequency of Del Sig ADC from the configuration parameters or vice versa in PSoC 3/5? | Cypress Semiconductor
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Calculating the maximum input signal frequency of Del Sig ADC from the configuration parameters or vice versa in PSoC 3/5?
How to calculate the maximum input signal frequency for Delta-Sigma ADC from the configuration parameters in PSoC 3/5?
Please use the following formulae to calculate the maximum input signal Band Width for Delta-Sigma ADC in PSoC3:
1. ADC_Rate = ADC_Clock / Decimation_Rate.(samples/second)
2. Band Width = ADC_Rate * 0.22 (0.22 because of the sinc4 filter in Decimator) (Hz)
Note: The miminum and maximum allowed ADC_Clock frequencies are 128 KHz and 6.144 MHz (for resolution upto 14 bits) or 3.072 MHz (for resolution from 15 to 20 bits). For various Decimation rates/Over-Sampling ratios supported by PSoC3's Delta-Sigma ADC, Please refer this KB article.
Given: Minimum ADC Rate = 48 Ksps and input signal BW = 22 KHz
Calculation: ADC_Rate = Band Width / 0.22 = 22 K / 0.22 = 100 Ksps
In order to achieve 100 Ksps, the maximum resolution we can get is 14 bits in Continuous Conversion mode.
Therefore the clock required is ADC_Clock = ADC_Rate * Decimation_Rate = 100 K * 32 = 3200 KHz which is within the limit of 6.144 MHz for ADC Clock Range.