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Byte Power Down feature in MoBL SRAMs | Cypress Semiconductors

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Byte Power Down feature in MoBL SRAMs

Last Updated: September 01, 2011
Question: 

How does the Byte Power Down feature work in Cypress MoBL SRAMs ?

or If I de-assert both BHE# & BLE#, will my device get deselected ?

or Which devices have Byte Power Down feature available ?

Answer: 
The Byte Power Down (BPD) function, available in certain MoBL SRAM’s, makes the BHE#-BLE# combination act as chip enable when disabled together. This means that when BHE# and BLE# are disabled together, the chip is switched to standby mode in addition to the IO’s being tri-stated.

This is a useful feature in low power applications, as it reduces the power consumption of the device when the IO’s are tri-stated.

MoBL SRAM's that incorporate the above BPD function have a nomenclature of CY621x7x, while those that do not incorporate the above function have a nomenclature of CY621x6x.

For the devices that incorporate the BPD function (the CY621x7x series), the byte enable access time tDBE = tACE (since the BHE#-BLE# combination is like chip enable), while for the devices that do not incorporate this function (the CY621x6x series), the byte enable access time tDBE = tDOE (since the BHE/BLE combination is like output enable).

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