BUSY signals when cascading asynchronous dual-ports | Cypress Semiconductor
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BUSY signals when cascading asynchronous dual-ports
How should I use the BUSY signal in width expansion mode?
Why are there BUSY inputs and BUSY outputs?
Why is there a Master and a Slave dual-port?
Why would I need a slave dual-port?
The BUSY signals (which can be input or output) are provided for cases when you are cascading 2 or more dualports together by width. (i.e. connecting two x8 dual ports to create a single x16 bus)
To understand the usage of the BUSY signal, it is good to understand why it exists at all. Basically, when you are using one asynchronous dual port alone and you try to access the same location at the same time from both the Left and Right ports, arbitration logic within the device decides which port wins. When 2 devices are cascaded together to increase the width, both devices share the address pins. If both Left and Right ports try to access the same data location, there is a chance that the arbitration logic of the first dual port declares the Left port the winner while in the second dual port, the right port is declared the winner.
To prevent this from occuring, only one of the dual ports should decide the "winner" and "loser". This is the Master device. All other cascaded devices are then slave devices. Once the master decides which port won arbitration, the other port outputs a busy signal to the slave device.
For example, when both the left and right ports try to access the same location, the master device may declare the right port the winner and assert BUSY on the left port (BUSY = LOW). The slave device receives this signal to prevent the left port from writing.