Buffering Interrupts. | Cypress Semiconductor
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The datasheet states that once the external master initiates a read request, all interrupts are buffered and the next interrupt from the SX2 is exclusively meant for the availability of the data from the read register request. When the external master has initiated a read request, and the SX2 triggers an interrupt ,interrupt status byte is seen instead of the read register request. Once the interrupt is cleared the next interrupt triggered has the value of the read request. So,when does the interrupts actually begin to get buffered ?
Although it is true that all interrupts will be buffered once a command read request has been initiated, in very rare conditions, there might be a situation when there is a pending interrupt already, when a read request is initiated by the external master. In this case it is the interrupt status byte that will be output when the external master asserts the SLRD. So, a condition exists where the Interrupt Status Data Byte can be mistaken for the result of a command register read request. In order to get around this possible race condition, the first thing that the external master must do on getting an interrupt from the SX2 is check the status of the READY pin. If the READY is low at the time the INT was asserted, the data that will be output when the external master strobes the SLRD is the interrupt status byte (not the actual data requested). If the READY pin is high at the time when the interrupt is asserted, the data output on strobing the SLRD is the actual data byte requested by the external master. So it is important that the state of the READY pin be checked at the time the INT is asserted to ascertain the interrupt source.