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Behavior of READY pin of SX2 in bus-powered mode | Cypress Semiconductor

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Behavior of READY pin of SX2 in bus-powered mode

Last Updated: January 02, 2012

What is the exact behavior of the READY pin in bus-powered mode after the cable is inserted for SX2?


READY pin is an active high signal which indicates if the SX2 is ready to accept data from an external master. READY line is used when writing to the SX2 configuration registers, Endpoint 0 buffer or the descriptor RAM using the Command Interface of SX2. The Command Interface makes use of only 8 data lines (FD[7:0]). After SX2 receives one byte of data it pulls the READY pin low to inform the external master not to send any more information. When the SX2 is ready to receive the next byte, the SX2 pulls the READY pin high again. Therefore we have to check the READY line before writing to SX2 registers and write only if it is high.

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