Asynchronous clock warnings (STA) for a SPI based PSoC Creator project | Cypress Semiconductor
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Asynchronous clock warnings (STA) for a SPI based PSoC Creator project
Question: I'm getting around 11 STA warnings when I compile a PSoC 3/5 project with SPIM & SPIS. What is the significance of these warnings?
Following is the pattern of warning message which you may get: (clock1, clock2, reg1 & reg2 are for example)
sta.M0011: Clock "clock1" at "reg1" is asynchronous to clock "clock2" at "reg2".
Descrption for this warning message: (PSoC Creator Topics)
The static timing analyzer could not detect the relationship between the clocks. To cross clock domains safely, use a synchronizer.
Actual Reason for this warning message:
For SPI Master as well for SPI Slave, the input synchronized option in the Input pins has to be unchecked. But PSoC Creator 1.0 can't detect that this is a valid configuration and it will use the Static Timing Analysis similar for a normal design. As the input pin is not snychronized to internal BUS CLOCK, STA tool will detect this asynchronous connection and hence the warning
This is applicable to MISO (SPIM) & MOSI, SCLK, SS (SPIS) input pins:
So it is safe to ignore these warning messages.
Note: If you are getting setup time & slew violation related warning messages, Please refer to this KB.