Asserting PKTEND pin when endpoint buffer is full in FX1/FX2/FX2LP | Cypress Semiconductor
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Asserting PKTEND pin when endpoint buffer is full in FX1/FX2/FX2LP
There is a note in the technical reference that states to never assert PKTEND on a full FIFO. If I have a quad buffered system and I put the last byte into the last packet, causing FULL flag to assert (operating in manual mode) can I not assert PKTEND commit the 4th packet to USB?
Section 9.2.5 (Control Pins (SLOE, SLRD, SLWR, PKTEND, FIFOADR[1:0])) states the following:
"The PKTEND pin must not be asserted unless a buffer is available, even if only a zero-length packet is being committed. The ?full? flag may be used to determine whether a buffer is available."
The above basically means that if there is no more buffer available in the interface domain (no buffer to commit) then the PKTEND pin must not be asserted.
In auto mode, when the last buffer of the multi buffered endpoint, for ex: 4th buffer of a quad buffered endpoint (or the 3rd buffer for a triple buffered endpoint, or 2nd buffer of a double buffered endpoint), reaches the number of bytes as set in the AUTOINLEN register (when endpoint operating in Auto mode), the packet will be committed automatically and the full flag will be asserted to indicate that there is no buffer space available.
In manual mode, the full flag will only be asserted when the last byte of the last buffer (in the case of the example above the 512th/1024th bytes of the fourth buffer) is clocked into the FIFO, the FULL flag will go high. The PKTEND CAN be used to commit this last (4th) packet of the quad buffered endpoint.